Hello!
Available soon.
Would not it be good to develop it?
http://uk.farnell.com/stmicroelectronic ... m%2Fsearch
STM32H743ZI
Key Features
Core
32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing one cache line to be filled in a single access from the 256-bit embedded Flash memory; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories
Up to 2 Mbytes of Flash memory with read-while-write support
1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
Dual mode Quad-SPI memory interface running up to 133 MHz
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash clocked up to 133 MHz in synchronous mode
CRC calculation unit
Security
ROP, PC-ROP, active tamper
General-purpose input/outputs
Up to 168 I/O ports with interrupt capability
Fast I/Os capable of up to 133 MHz
Up to 164 5 V-tolerant I/Os
Reset and power management
3 separate power domains which can be independently clock gated or switched off to maximize power efficiency:
D1: high-performance capabilities for high bandwidth peripherals
D2: communication peripherals and timers
D3: reset/clock control/power management
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode (5 configurable ranges)
Backup regulator (~0.9 V)
Voltage reference for analog peripheral/VREF+
Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging
Low-power consumption
Total current consumption down to 4 μA
Clock management
Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 40 kHz LSI
External oscillators: 4-48 MHz HSE, 32.768 kHz LSE
3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
Interconnect matrix
4 DMA controllers to unload the CPU
1× high-speed general-purpose master direct memory access controller (MDMA) with linked list support
2× dual-port DMAs with FIFO and request router capabilities
1× basic DMA with request router capabilities
Up to 35 communication peripherals
4× I2C FM+ interfaces (SMBus/PMBus)
4× USART/4x UARTs (ISO7816 interface, LIN, IrDA, modem control, up to 12.5 Mbit/s) and 1x LPUART
6× SPIs, including 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 133 MHz)
4x SAIs (serial audio interface)
SPDIFRX interface
SWPMI single-wire protocol master I/F
MDIO Slave interface
2× SD/SDIO/MMC interfaces (up to 125 MHz)
2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
2× USB OTG interfaces (1FS, 1HS/FS)
Ethernet MAC interface with DMA controller
HDMI-CEC
8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
3× ADCs with 16-bit max. resolution (14 bits 4 MSPS, 16 bits 3.6 MSPS)
1× temperature sensor
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (8 MHz bandwidth)
1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
Graphics
LCD-TFT controller up to XGA resolution
Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load
Hardware JPEG Codec
Up to 22 timers and watchdogs
1× high-resolution timer (2.5 ns max resolution)
2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 200 MHz)
2× 16-bit advanced motor control timers (up to 200 MHz)
10× 16-bit general-purpose timers (up to 200 MHz)
5× 16-bit low-power timers (up to 200 MHz)
2× watchdogs (independent and window)
1× SysTick timer
RTC with sub-second accuracy & HW calendar
Debug mode
SWD & JTAG interfaces
4 Kbyte Embedded Trace Buffer
True random number generators (3 oscillators each)
96-bit unique ID