Hi,
I would like to run a PIC24FJ256GA406 at 96MHz using the internal FRC Oscillator with PLL. One issue is that FC7.3.0.6 will not allow a Clock speed(Hz) setting (Build\Project Options\General Options) of anything above 32MHz, for this PIC.
As the datasheet states that the "default divisor of the postscaler is 2, which will generate a 4 MHz clock to the PLL module", I assumed that the FRC was running at 4MHz. I set the system clock to 32Mhz, i.e. FRCPLL and fixed PLL x 8, (Clock speed(Hz) set at 32MHz). With these settings everything works correctly. The LED flasher circuit flashes correctly at 1 Hz and the frequency measured on OSCO is 16MHz (FOSC/2). The baud rate on my PCB was also correct when tested against an external device. The flowchart is attached.
If I use the FRCPLL and "96MHz is selected,oscillator input multipied by 24 (4 MHz input)" option, would this give me a 96MHz system clock, as long as the Clock speed (Hz) setting in Build\Project Options\General Options could be set at 96MHz? I would appreciate any assistance wrt setting this up correctly and also how to bypass the clock speed limitation being imposed by FC7, currently.
Thanks.
Leo
PIC24 Internal CLocking
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Re: PIC24 Internal CLocking
Hi Leo,
You could edit 24FJ256GA406.fcdx found in:
C:\Program Files (x86)\Flowcode 7\FCD\PIC16 (64 bit windows)
C:\Program Files\Flowcode 7\FCD\PIC16 (32 bit windows)
At the top of the file you will see:
Just change clock max_speed value
Personally I use notepad ++ as it will enable you to save in admin mode, even if not in admin mode to start with.
You could edit 24FJ256GA406.fcdx found in:
C:\Program Files (x86)\Flowcode 7\FCD\PIC16 (64 bit windows)
C:\Program Files\Flowcode 7\FCD\PIC16 (32 bit windows)
At the top of the file you will see:
Code: Select all
<root>
<device name='24FJ256GA406' product='PIC16' family='24F' bits='16' >
<clock max_speed='32000000' master_divider='2' default='12000000' />
Personally I use notepad ++ as it will enable you to save in admin mode, even if not in admin mode to start with.
Martin
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Re: PIC24 Internal CLocking
Hi Martin,
Thanks for the response.
I've edited the file and can now set the clock speed to 96 MHz, but unfortunately even when selecting the 96 MHz PLL x 24 option the system clock seems to be running at 32 MHz, i.e. frequency measured at OSCO = 16 MHz.
I've had a look at trying to set up the internal clocking via a C code block as you've suggested in previous posts, but I just don't know enough C to be able to do that. Is there another way from within FC7?
Kind regards.
Leo
Thanks for the response.
I've edited the file and can now set the clock speed to 96 MHz, but unfortunately even when selecting the 96 MHz PLL x 24 option the system clock seems to be running at 32 MHz, i.e. frequency measured at OSCO = 16 MHz.
I've had a look at trying to set up the internal clocking via a C code block as you've suggested in previous posts, but I just don't know enough C to be able to do that. Is there another way from within FC7?
Kind regards.
Leo
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Re: PIC24 Internal CLocking
Hi Leo,
I've not had time to dig in for your specific device but this is the type of C code we use to enable/configure the PLL.
PIC24F / dsPIC33F
PIC24EP / dsPIC33EP
I've not had time to dig in for your specific device but this is the type of C code we use to enable/configure the PLL.
PIC24F / dsPIC33F
Code: Select all
//On the PIC24FJ64GB004 Family of USB microcontrollers, the PLL will not power up and be enabled
//by default, even if a PLL enabled oscillator configuration is selected (such as HS+PLL).
//This allows the device to power up at a lower initial operating frequency, which can be
//advantageous when powered from a source which is not gauranteed to be adequate for 48MHz
//operation. On these devices, user firmware needs to manually set the CLKDIV<PLLEN> bit to
//power up the PLL.
MX_UINT16 pll_startup_counter = 600;
CLKDIVbits.PLLEN = 1;
while(pll_startup_counter--);
Code: Select all
//Setup configuration for 70MIPs using 8MHz Crystal
PLLFBD = 68; // M=70
CLKDIVbits.PLLPOST = 0; // N1=2
CLKDIVbits.PLLPRE = 0; // N2=2
OSCTUN = 0; //Tune FRC oscillator, if FRC is used
//Disable Watch Dog Timer
RCONbits.SWDTEN = 0;
// Clock switching to incorporate PLL
__builtin_write_OSCCONH(0x03); // Initiate Clock Switch to Primary
// Oscillator with PLL (NOSC=0b011)
__builtin_write_OSCCONL(0x01); // Start clock switching
while(OSCCONbits.COSC != 0b011);
// Wait for Clock switch to occur
while(OSCCONbits.LOCK != 1);
//USB H/W initialization for 70 MIPs
ACLKCON3 = 0x24C1;
ACLKDIV3 = 0x7;
// Wait for PLL to lock
ACLKCON3bits.ENAPLL = 1;
while(ACLKCON3bits.APLLCK != 1);
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Re: PIC24 Internal CLocking
Hi Leo,
I think the System Clock speed of the processor can not be higher than 32MHz, because in the PLL system block has a divider, that always divided by 3 the clock signal from 96 MHz output.
Kind regards,
Lagoda
I think the System Clock speed of the processor can not be higher than 32MHz, because in the PLL system block has a divider, that always divided by 3 the clock signal from 96 MHz output.
Kind regards,
Lagoda
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Last edited by Lagoda on Thu Dec 06, 2018 7:00 am, edited 1 time in total.
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Re: PIC24 Internal CLocking
page 500 or section 36.1 of the device datasheet states the max instruction clock is 32MHz so yes it looks like the divide by 3 is fixed.
Regards Ben Rowland - MatrixTSL
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