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if i enable pwm 2 on E0 i get with a 10k pulldown 100mv of pwm signal on E1 and A5
when using i2c with 1k pullups and 10k pulldowns the clock cuts into the sda line at certain periods
in the picture the traces dont appear be a problem in the way they are layed out it appears to be at the chip legs
i have 6 .1uf caps spread around the board,
adding additional grounds, powers and caps of different values do not change condition
1k pulldown resistors pretty much eliminate phenomenem but thats to low of a resistance
was wondering your thoughts on this if it is normal or are there special measures that i should do to prevent this error on next pcb run
the last board with a 28 pin soic didnt have any sign of these issues and had longer traces that are just as close together?
https://dl.dropbox.com/u/10367218/100_0992.JPG
https://dl.dropbox.com/u/10367218/100_0993.JPG