Hello
I found the tool that converts from schematic design to vhdl, file > create/update > create HDL design file for current file, but errors has occurred, and the part of 7 segment has errors too, the following code shows my simple program to display on "EB008 Quad 7-segment", entering the binary number using switches and displaying this number on 7 segment, the part of annodes is not correct, so how to solve it.
my regards
LIBRARY ieee;
USE ieee.std_logic_1164.all;
Library work;
-- Title "7 segment display driver circuit";
-- File: seg7.vhd
ENTITY seg7 IS
PORT (d : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);-- 7 segment outputs
annodes : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --4 signals of J2
END seg7;
ARCHITECTURE display OF seg7 IS
BEGIN
s <= "11000000" WHEN d = "0000" ELSE -- H"40"
"11111001" WHEN d = "0001" ELSE -- H"79"
"10100100" WHEN d = "0010" ELSE -- H"24"
"10110000" WHEN d = "0011" ELSE -- H"30"
"10011001" WHEN d = "0100" ELSE -- H"19"
"10010010" WHEN d = "0101" ELSE -- H"12"
"10000010" WHEN d = "0110" ELSE -- H"02"
"11111000" WHEN d = "0111" ELSE -- H"78"
"10000000" WHEN d = "1000" ELSE -- H"00"
"10010000" WHEN d = "1001" ELSE -- H"10"
"10001000" WHEN d = "1010" ELSE -- H"08"
"10000011" WHEN d = "1011" ELSE -- H"03"
"11000110" WHEN d = "1100" ELSE -- H"46"
"10100001" WHEN d = "1101" ELSE -- H"21"
"10000110" WHEN d = "1110" ELSE -- H"06"
"10001110"; -- H"0E"
END display;
7 segment in VHDL help
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